1. Field of the Invention
This invention relates generally to semiconductor manufacturing, and more particularly to providing an algorithm and method to determine whether dose, temperature, or both need to be adjusted to achieve a desired critical dimension (CD) for contact holes and vias below the resolution capabilities of the photolithographic process utilizing a post-lithography “reflow” process.
2. Description of the Background
In processes for producing semiconductor devices from a semiconductor wafer, a number of techniques have been developed in order to form circuit patterns on the wafer. One of these processes employs photolithography, which defines the circuit features on a wafer according to a specified pattern or mask. Subsequent manufacturing steps that are used to form a device include chemical and physical film depositions, etching, ion implantation, diffusion, annealing or thermal oxidation. The process for patterning the photoresist is referred to as a photolithography process, which implies first depositing a uniform layer of photoresist or polymeric material onto the substrate, next exposing the photoresist layer to optical illumination through the mask, and then developing the exposed photoresist layer. For example, a UV radiation source (generally either 193 nm, 248 nm or 365 nm wavelength laser-generated radiation—somewhat below the visible spectrum of light) is propagated through a mask to selectively start a photo-chemically initiated reaction in which exposed portions of the coating are rendered soluble to a developer. The combined intensity of the energy multiplied by the time for which it is applied is referred to as the “dose,” and is usually expressed in millijoules/cm2. When the developer rinses the coating, it washes away the areas that were exposed, leaving a three-dimensional relief image in the coating. This imaged coating layer is used as a template to selectively perform operations on the exposed substrate. The case described above is for a positive tone resist where the exposed material becomes soluble in developer. If the imaged coating layer or resist becomes insoluble in the irradiated regions it is termed a negative tone resist. The development step may be carried out using wet chemical etching, dry plasma etching or by conversion to a volatile compound through the exposure radiation itself. The exposure radiation may be in the form of visible, deep ultraviolet or x-ray photons, or electron or ion beams of particles. The exposure can be made by a parallel process such as contact or projection printing from a mask, or by serially scanning one or more beams.
Each generation of semiconductor chips has denser circuit patterns with a greater number of devices requiring finer and smaller dimensions. This drive for miniaturization often exceeds the capabilities of the present generation of exposure tools used in the lithographic process that define the circuit geometries. To overcome some of the present limitations of the lithographic process a post-lithography “reflow” process is often employed.
As the dimensions of contact holes and vias decrease below the resolution capabilities of resists, shrink methods such as post-lithography “reflow” are increasingly being used to achieve the desired contact hole sizes. One of the more promising shrink techniques is thermal flow where after imaging a hole, the hole is shrunk to the final target size by heating the wafer above the flow temperature of the resist material. Through proper materials design of the resist, it is possible to induce a controlled “melt” of the material that shrinks the hole size to a desired target dimension. Although we discuss the shrinking of holes, other types of spaces in resist can also be shrunk. These can include elongated holes or trenches.
FIGS. 1A and 1B illustrate post-lithography “reflow” to form a reduced hole feature. The initial exposure dose in the lithographic process defines the image size (H, W) of the hole feature 100 in FIG. 1A. In FIG. 1B, the final image size (H′, W′) of the hole feature 100′ is defined by the combination of the exposure dose of the initial image of FIG. 1A, followed by a temperature profile applied to reflow the hole feature 100 to the dimensions of hole feature 100′. A simple temperature profile would include the ramp rate up to the flow temperature, the dwell time at the flow temperature and ramp rate down to room temperature. More complicated temperature profiles can also be used. For a typical positive tone resist system, increasing the exposure dose with a given mask results in larger hole widths (W). Conversely, increasing the temperature during reflow will result in a reduced hole width (W′) through the reflow step.
A critical aspect of the post-lithography “reflow” is process control. Both the dose and temperature responses are known to vary over time and require regular feedback control. An obvious solution would be to simply measure the first image formed during the lithographic process (dose), provide feedback for a new dose for subsequent lots, and feed-forward the critical dimension (CD) error to pre-correct the reflow process accordingly to compensate. However, this approach to process control has significant drawbacks. First, the measurement of these critical dimensions (CD) is time consuming. Second, CD metrology in modern semiconductor manufacturing processes is performed with specialized scanning electron microscope tools, and would require stopping the process following exposure and development to obtain the developed image, by removing the wafer and placing it in the microscope. After the CD metrology is completed the wafer would then be returned back to the lithography tool (where lithography tool refers to the “track” where the post expose processing occurs) to perform the final reflow step. The additional handling and moving of the wafer can introduce additional potential defects to the process.
Simply measuring the final CD after flow is also unsuitable as there are two potential sources of error, both of which are equally important to control, and measuring a single arbitrary feature as is done in the current art is inadequate to separate and determine the impact of the two potential sources of error—dose and temperature. This shortcoming can be seen in current CD control algorithms, which adjust dose alone even though the CD error could have come from a change in the flow characteristics of the resist. Specifically, if the CD is off target due to a difference in the flow temperature point of a new batch of resists, the current CD correction algorithm will incorrectly adjust the dose to try to compensate.
FIG. 3 illustrates the current process of two separate CD metrology steps (306, 310) to independently quantify feedback to both exposure (dose)/image development process 304 and thermal reflow (temperature) process 308, respectively, after a one-time initial process characterization 300 is defined for incoming product 302. If the CD is at its target value 312, the wafer is considered done 314 and proceeds further within the manufacturing process. However, if the CD is not at it target value 312, the image is stripped from the wafer, and the process of re-imaging the wafer 304, and carrying out the post-lithography “reflow” 308 is repeated with the feedback correction values.